The present invention relates to a method and/or architecture for charge pumps generally and, more particularly, to a method and/or architecture for a bi-directional, high-voltage, cross-coupled charge pump.
Programming or erasing a non-volatile memory array usually requires high voltages. The value of the high voltages depends on the type of technology used to implement the non-volatile memory. The high voltage can be a positive high voltage, a negative high voltage, or both. For example, silicon, oxynitride, oxysilicon (SONOS) technology requires a high positive voltage (typically 9V to 10V) to program SONOS memory cells and a high negative voltage (typically xe2x88x929V to xe2x88x9210V) to erase SONOS memory cells. Charge pump circuits are typically implemented in memory circuit designs to generate the required program and erase high voltages.
Referring to FIG. 1, a diagram of a circuit 10 illustrating a conventional charge pump is shown. The circuit 10 illustrates a so-called Dickson charge pump circuit (see J. F. Dickson, xe2x80x9cOn-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Techniquexe2x80x9d, IEEE J. of Solid-state Cir., vol SC-11, No. 3, June, 1976, pp. 374-378, which is hereby incorporated by reference in its entirety). The circuit 10 includes a number of stages 12a-12n. Each stage 12 contains a diode connected transistor 14 and a capacitor 16.
The circuit 10 can provide a supply voltage minus threshold voltage (Vccxe2x88x92Vtn) increase at each stage. The output voltage Vpp of the circuit 10 can be Vpp=approximately (Vccxe2x88x92Vtn)*n+Vcc. The circuit 10 is shown implemented using a positive input voltage Vcc and NMOS transistors 14a-14n. The circuit 10 generates a positive voltage Vpp. However, the circuit 10 can be implemented using a negative input voltage and PMOS transistors to generate a negative output voltage Vpp.
For technologies requiring both positive and negative high voltages to program and/or erase the non-volatile memories (i.e., SONOS technology), the conventional methodology is to provide two separate high voltage charge pumps: a first to provide the high positive voltage and a second to provide the high negative voltage. The conventional charge pump designs for programming and erasing the non-volatile memories have the disadvantages that (i) two charge pump circuits require significant die area (twice the area of a single charge pump) and (ii) each charge pump is only used approximately 50% of the time since programming and erasing do not occur simultaneously.
It would be desirable to have a method and/or architecture for generating both positive and negative high voltages using a single charge pump circuit.
The present invention concerns an apparatus comprising a circuit configured to generate an output voltage having a magnitude greater than a supply voltage, where the output voltage is (i) a positive high voltage when a first input is in a first state and a second input is in a second state and (ii) a negative high voltage when the first input is in the second state and the second input is in the first state.
The objects, features and advantages of the present invention include providing a bi-directional architecture for a high-voltage, cross-coupled charge pump that may (i) generate either a high positive output voltage or a high negative output voltage, (ii) have reduced charge pump die area, (iii) minimize body effect, (iv) improve efficiency, (v) perform well at low supply voltages, (vi) perform well with supply voltages greater than threshold voltages (VCC greater than Vtn), (vii) require fewer pump stages than a conventional design, (viii) reduce the need for pump transistors having higher breakdown voltage, (ix) eliminate diode drop at the output stage, (x) be implemented using small pump switch transistors, (xi) have reduced capacitor load, and/or (xii) be implemented with a variety of high voltage charge pump designs.